Conventionally, wire bonding by gold wire have been used to mount semiconductor chips on printed circuit boards. The gold wire is connected on both ends with electrodes located on the semiconductor chip and the printed circuit boards.
As the lead count of semiconductor chips increases, and the pad pitch on the chip decreases, the pad pitch on the printed circuit boards is decreasing. Hence, the pad density of the recent printed circuit boards is so high that it is almost impossible to manufacture with the ordinary printed circuit board technology. Multilayer boards and multiple bonding shelves have been developed to alleviate the pad density on the printed circuit boards.
These printed circuit boards have been made by technologies such as laminating boards having preformed larger and smaller openings and by fabricating a printed circuit board with bonding shelves (e.g. Japan Examined Patent 2-5014, Japanese Examined Patent 5-41039), or by laminating pre-fabricated cores to form multilayer boards, and etching the opening by a laser (applied by the inventor hereof, Japanese Application Patent 7-171391).
The conventional printed circuit boards having multiple bonding shelves mentioned above were complex in manufacturing technology, and also costly, and a less expensive process is desired. On the other hand, some problems were left in wire bonding, since the multiple bonding pads had level differences.
The present invention aims to solve the problems inherent in conventional printed circuit boards. The objective of this invention is to provide printed circuit boards for mounting semiconductor chips which can be fabricated in a simple manner with inexpensive cost while maintaining high density bonding pads, and also keeping the level difference to a minimum to make wire bonding easy.
Area grid array package technology has expanded in recent year as a technology to connect semiconductor chips and printed circuit boards. This technology at times called a ball grid array (BGA) or chip size package, aims to make connection with a printed circuit board, called a "mother board", by conforming grid pads, and putting solder balls or solder paste on these pads. This technology is described in the book "Ball Grid Array Technology" edited by John H. Lau and published by McGraw Hill in 1995.
In the conventional area g rid array package, as shown in FIG. 7, circuits 3, 4 are formed on both sides of the insulative base material A, and the circuits 3,4 are connected with through-holes 22. On the back side of the base material A, pads 9 are arranged in a grid, and solder balls 11 are located thereon. On the surface of the base material A, a semiconductor chip 5 is mounted, which is connected with each circuit 3 by bonding wires 14. The semiconductor is encapsulated by a molding resin 19.
However, in the above conventional structure, the area grid array package had one side to attach the semiconductor chip and the other side to attach solder balls. Hence, all traces (metallization/conductive paths) usually had to be routed from the top to the back side. To attain this, through-holes have been needed on the external edges. Since these through-holes are usually mechanically formed, they are costly, and they have a smaller pitch in higher pin count packages and have higher density packages to attain a pre-designed size. Thus decrease of yield and electromigration were liable to occur.
To solve these problems, some technologies have been disclosed such as Japanese Opened Patent 7-74281 . In this patent, via-holes were used to connect the first surface and the second surface, and connection was made by plating the via-holes. This allows direct connection between the pad and the first surface, and the routing issues are very much alleviated. However, this technology also required formation of via-holes connecting the first surface and the second surface. This limited density of the circuits and caused high cost.
Another proposal by the inventor hereof Japan Application Patent, H8-78261 and shown in U.S. application Ser. No. 08/811,810, now abandoned, is seen in FIG. 8, wherein a flexible tape A such as polyimide tape is used as a insulative base material, and circuits 3 (also called circuitry metallizations or traces) are formed on the first surface 1, a semiconductor chip 5 is mounted on the same surface, and connection pads 6 on the first surface 1 are connected to the semiconductor chip 5 by bonding wires 14. The package is molded using a molding resin 19 such as an epoxy resin, and solder balls 10 are attached to boarding pads 8 in an opening 13 formed from the second surface 2. This structure is advantageous in attaining higher density and lower cost, since the openings for the solder pads are made in the tape A itself, and there is no need for solder resist to prevent flowing of solder in reflow soldering. However, because the substrate is just single sided, there are some limitation in pin count, and it is sometimes difficult to obtain extremely high density.
Other proposals (e.g. Japanese Open Patent 7-321250, U.S. Pat. No. 5,420,460) were made (FIG. 9), in which flexible synthetic tapes A such as polyimide are used instead of rigid laminates. In the second surface 2 circuits 4 are formed, and the substrate A is attached to the back side of heat slug 15 using an adhesive 21. A semiconductor chip 5 is mounted underneath the said heat slug 15 in a "Flip-chip configuration. Electrical connection is made between the semiconductor chip 5 and the pads 7 for connection with the semiconductor chip, encapsulated with a molding resin 19, and solder balls 11 are attached utilizing a solder resist mask 20 as seen in FIG. 9. This structure is useful, since routing on the tape can be only single-sided, and if patterning technology of TAB tapes are used, the tapes can have higher density than rigid laminates, and the above-mentioned difficulty in routing is very much alleviated. However, this structure has had a limitation as to pin count, and usually, 300-400 pins are a maximum.
A structure (FIG. 10) part of which is shown in U.S. application Ser. No. 08/811,810, now abandoned, includes circuits 3 formed on the first surface 1 of a flexible tape made of a synthetic resin such as polyimide as an insulative base material A, which is attached by an adhesive such as an epoxy, epoxy-acrylic or polyolefin adhesive to the back side of a heat slug 15 with the reverse side of the base material A having the circuit upward. A semiconductor chip 5 is attached underneath the heat slug 15 and connected electrically to the circuit traces with bonding wires 14. The chip and bond wires are encapsulated with a mold resin 19. Openings 13 are formed in base material A for attaching solder balls 10 from the second surface 2 of the tape A to solder ball pads. This structure has advantages because it does not need coating of photo-sensitive liquid solder resist to prevent flowing out of solder in reflow soldering, since the opening to the solder pad is made in the tape itself. Hence, it is easy to make higher density packages at a lower cost. However, since the structure had traces just on one side, the pin number was limited, and usually the maximum pin count was 300-400. Limitation of pin count was a problem.
Technologies of using a laser for the formation of printed circuit boards are used mainly to perforate via holes. The laser used here is either an excimer laser, a YAG laser, or an impact laser which is an improved carbon dioxide laser. The application of an excimer laser to the manufacturing printed circuit boards are described in Japanese Open Patent 5-136650, 5-152744, and 5-152748, and the application of impact laser to the manufacturing of printed circuit boards is described in "A Large Format Modified TEA CO2 Laser Based Process for Cost Effective Via Generation" (1994 International Conference on Multichip Modules, Apr. 13-15, 1994).